FPGA Design

Visualization of a pipelined instance of the foldl function

1 bT
2 :: KnownNat n
3 => Vec (n+1) a
4 -> (a->a->a)
5 -> Vec (n+1) a
6 -> a
7 -> (Vec (n+1) a,a)
8 bT xs f rs a = (rs',o)
9 where
10 o = last rs'
11 rs' = zipWith f (a +>> rs) xs
12
13 -- Initialisation:
14 b
15 :: HiddenClockReset domain gated synchronous
16 => Num a
17 => Signal domain a
18 -> Signal domain a
19 b = mealy (bT (1:>2:>3:>Nil) (+)) (repeat 0)

“CλaSH is a real pleasure to use compared to VHDL. Being able to use Haskell’s strong type system really helps speed up development. Modules written in CλaSH are not only easier to maintain, but also easier to compose with one another.”

Joe Hermaszewski – Myrtle Software

Our projects

Project title

Project title

Project title

An FPGA design house delivering "right the first time" solutions.

Design and realisation by:
Comyoo | creatieve studio

Address


Institutenweg 25A
7521 PH Enschede
+31 (0)85 8000 380
info@qbaylogic.com


CoC: 66440483
VAT: NL856554558B01