Speakers:
Dr. Ir. Edwin Hakkennes (Technolution)
Ir. Tom van Leeuwen (Technolution)

Abstract:
At Technolution, we place a lot of emphasis on the quality and reproducibility of our FPGA design process. Design automation is an important method to ensure these aspects, right from the start of any FPGA development project.

In this talk, we will show you the key elements of the Technolution way of working for FPGA development and related disciplines such as electronics design and (embedded) software development. We will start with setting out our main goals, as well as the rules and tools we apply to realize these goals. In conclusion, we will demonstrate the benefits of this approach. In particular, we will show you how to use Gitlab to automate the testing, building and releasing of our implementations. We will look at some of the tools we developed along the way. Finally, we will show how all of this helps us work efficiently and effectively for our customers.

Speaker:
Dirk van den Heuvel (TOPIC embedded systems), Principal Consultant

Abstract:
The time FPGAs were used just as glue-logic or as a prototyping means for ASICs has long gone. The current generation FPGA and SOC devices form the core of applications in a variety of domains. This demands of a product not just to comply to the requested functionality, but also to specific standards and legislation. Safety and security are often key product aspects as they relate to product risks. Many development standards are therefore typically risk-based. Compliance to these standards has a significant impact on the functional design and the additional features to implement.

 This presentation will address the safety aspects of some typical FPGA/SOC-based designs and applied design flows where functional safety formed an integral part of the implementation. Function isolation, processing diversity, single-event upset detection and mitigation are being discussed here in an end-product context. Join this presentation to learn from hands-on experience how to reduce the impact of safety-related design decisions and applied development flow.

Speaker:
Ronald Grootelaar (Kendrion)

Abstract:

• High performance signal processing in low-cost FPGAs
• Optimization for performance and resource utilization
• Design & I/O constraints and timing closure
• Best practice and tips & tricks

Speaker:
Joachim Mueller (Efinix), FAE Manager Europe

Abstract:
The second generation FPGA family introduced by Efinix Inc (Cupertino, California), Efinix Titanium, consistently continues the path of solving special requirements for edge applications and beyond.
Small size, low power, support for special functions. The presentation takes a tour through Titanium functions and features. Why is Titanium is a good choice for the edge, for sensor aggregation, for pre-processing and more? The session will conclude with an up-to-date snapshot of upcoming family members and variants.

Speaker:
Frank de Bont (Core|Vision)

Abstract:
The latest generation of AMD FPGAs are very complex  systems. As an example I will mention a Versal AI FPGA. The Versal device has 3 processing engines called: Scalar
Engines, Adapatable Engine and Intelligent Engines. Each processing engine can communicate with each other via a Network On-Chip.
To achieve a design closure more efficiently and productively, we must use the three
pillars of design closure (functional closure, timing closure and power closure).
This presentation will emphasis on timing closure. We will address the following topics in a nutshell

• complex timing constraints,
• virtual clocks,
• multi-cycle paths,
• crossing of clock domains crossing
• SLR transitions.
  

Speaker:
Etienne Janssen (Lattice Semiconductor)

Speaker:
Martijn Bastiaan (QBayLogic)

Abstract:
This talk will discuss the Clash hardware description language with a focus on verification. We will begin by providing an overview of the Clash HDL, highlighting its distinct features compared to traditional HDLs. The presentation will then quickly focus on property testing and constraint random generation and its role in creating diverse test scenarios. While constraint random generation is something that is commonly found in many verification frameworks, the automated shrinking of counter-examples as available in some of Clash verification frameworks is not. Practical examples will be presented to demonstrate the application of these techniques in the verification process and their potential to enhance design reliability and efficiency.

Speaker:
Gert-Jan Lahpor (Aimvalley), Senior FPGA designer

Abstract:
AMD supports a Dynamic Function eXchange FPGA development flow which allows partial implementation and programming of FPGAs.
A variant of this flow is called “abstract shell”. It’s focus is on partial implementation and not so much on partial  programming of the FPGA.
The abstract shell flow can also be used to gain better control over timing-closure. As a bonus it can significantly reduce FPGA build times.
This presentation will elaborate on the benefits and drawbacks of this technique