When you believe it is a challenge and a hassle to program an FPGA, you haven’t experienced the benefits of our innovative model-based methodology yet. Every step in the whole process is done in one and the same language. This leads to FPGA solutions that are first time right, while avoiding management problems of co-ordinating various teams working with different programming languages. So, there will be no more endless project delays and cost overruns. Instead, you will experience a significantly shorter time to market. How can we promise you all this? Let’s find out how we work at QBayLogic and then you can decide for yourself if you would like to challenge us.
The first step obviously starts with your idea for an application. We really take the time to discuss your idea, so that we have a precise and mutual understanding of what it is you need. Based on all findings, we subsequently create a precise model of your application. Because that model is formally expressed in our system, it has the additional advantage of being executable and testable. And very important, it gives us a golden reference to check later design steps. Upon request, we can also generate an executable for your own computer system so that you can experiment with it, in your own time and on your own computer. We can even create visualizations of the hardware, we have yet to develop.
The created model is the basis for the following step: developing a solution and programming an FPGA. We remark that all intermediate design steps, including optimisations, are performed in the same language as in which the model is described. Therefore it’s possible to express hardware details down to the register level. In other words, we have full control over the performance of the architecture during the design process. This is an important difference with common high level synthesis approaches, which are usually based on a mainstream programming language and offer little control over the performance of the hardware.
Another important advantage of expressing all design steps in one and the same language, are the sophisticated verification possibilities. Furthermore, our fundamentally model based design methodology is supported by a modern programming environment, which offers a strong typing system and automated and randomized testing mechanisms popularized by the programming language Haskell. Hence, errors are discovered at an early stage, even before simulating, which reduces the development costs considerably.
Once we arrive at the final stage of the design, we can again generate an executable for your own computing system. This gives you the possibility to experiment with the resulting design in a cycle accurate manner, which gives an exact insight in the performance of the design. Only when the final design answers all its requirements, we generate VHDL or Verilog, so that the design can actually be put on an FPGA.
Off course we will stay in close contact with you, during the entire design and testing process. Your satisfaction is very important for us. And as we’ve mentioned before, our methodology guarantees you upfront, that the project will remain within agreed limits regarding both time and budget.