Terabit laser communication

As part of ESA’s Terabit Optical Communication Adaptive Terminal project, TNO and Demcon developed a wavefront sensor able to capture images at a high sample rate. Traditional processors fell short due to the chip’s high-bandwidth output. QBayLogic contributed by developing the RTL design capable of processing these streams on an FPGA instead.

This project has been covered by an article in Bits&Chips.

The challenge

This project aims to tackle the ever-increasing need for bandwidth in ground/satellite communications. In this particular case, TNO and Demcon sought to tackle this through optical means — using high energy laser beams. As with any optical communication, the signal’s deformation is highly dependent on the medium it travels in. To counteract this deformation, TOmCAT continuously measures and compensates for it. This process is highly sensitive to timing: a receiver needs to finalize processing an incoming sample at most 3μs after the sensor has sent the image. Typically, traditional processors are not well-suited for these types of deadlines and bandwidths — hence the need for an FPGA.

Our approach

At QBayLogic, we use a model-based methodology to design FPGA architectures for accelerators. We started by interpreting the problem in its purest form: a mathematical specification. In this case, the specification described operations on a matrix representing an image. We trivially converted the specification into an executable model, using Clash. This model served as our golden reference throughout the design process.

Step by step, we transformed the model into something that suits the target device’s characteristics and the format of the incoming data. Thanks to Clash, we can design the model, all its intermediate steps, and the result in the same language. The fact that it is developed in Clash means we can trivially simulate the architecture anywhere in the design process and check it against the original model. This dramatically reduced the potential for errors and helped us deliver a reliable product on time.

To read more about our design process in general, read “Our design process”.

Our deliverable

Of course, having a great design is of no use if it cannot be integrated with existing designs and languages. But thanks to Clash, we can generate traditional HDL files from our optimized design. On time; and right-first-time.

For further information on the TOmCAT project, head over to ESA’s website.

An FPGA design house delivering "right the first time" solutions.

Design and realisation by:
Comyoo | creatieve studio


Capitool 10
7521 PL Enschede
+31 (0)85 8000 380

CoC: 66440483
VAT: NL856554558B01