For decades it is common practice to design digital hardware architectures in VHDL or Verilog. To overcome the struggling with the low-level nature of these languages, there have been many attempts to generate VHDL / Verilog from normal programming languages (C++, Python, etc). Unfortunately, none of these so called high-level synthesis tools give a satisfying result. Furthermore, other languages are often still needed, for example for modelling, for verification and for communication with a standard CPU.

At QBayLogic we are convinced that this makes no sense: mainstream languages are simply not suitable to express hardware concepts. Besides, the use of separate languages often leads to differences in functionality. This causes both a technical and a managerial nightmare.

Instead, we offer an alternative for all this time-consuming and error-prone hassle: no more endless design optimizations by trial and error, no more simulation inaccuracies, no more project delays and cost overruns. Our solution is based on the language that we use, which is functional in nature. We can express and run a formal model of the design problem at hand, which offers a golden reference. But not only that, our functional language can also express FPGA details which allows us to control performance.

Further substantial advantages of our approach are for example, that all intermediate design steps can be tested quickly and compared to the golden reference. Also the software environment of our functional language offers support for early error detection, such as type-checking and automatic test generation. And last but not least both the behaviour of, and the communication with all other components of a system, such as external memory or an ARM processor on the FPGA board, can be expressed in this single functional language.

The importance of the above can hardly be overstated. In fact our methodology is unique and fundamentally model-based, hence avoiding many of the design issues mentioned before.