We get it right the first time. QBayLogic helps R&D and engineering teams stuck on latency, throughput, or security. Proven correct with formal methods and our own compiler, Clash.
OUR CLIENTS
When your engineers, your technology, or a general FPGA shop reaches its limit.
01 / Get unstuck
When a previous approach has failed, or your team lacks the specialist depth to hit the deadline. We have solved this class of problem before.
02 / A real method
When off-the-shelf parts fall short and you need a custom route. Clash and functional programming get you a working prototype early, not legacy guesswork.
03 / Proven right
When security or certification is a requirement you must prove, not just claim. Formal verification, demonstrably correct against the specification.
Most FPGA and ASIC work is still done the old way, hand-verified and hoped. We work differently. Clash, our own compiler, brings functional programming to hardware, and formal methods prove the design is correct.
A 3µs deadline at 5000 fps, met on an FPGA. Our RTL for TOmCAT, ESA’s terabit optical link, with TNO and Demcon.
Smart cards with mathematically proven security properties. Our Clash work for EvIT, Cyberagentur’s verification mission.
Verification that catches problems early, not late. We rebuilt Axign’s flow around CI and simulation tooling for their next-gen audio chips.
Eight FPGA boards, optically linked, synced to the nanosecond. Our proof-of-concept hardware and software stack for Bittide, Google’s research ...
Long-term partners in secure, high-speed communication who trust us when the result has to be right.
Who we are
We grew out of the University of Twente, the birthplace of our Clash compiler and a leading European centre for chip and embedded-systems research. Our expertise runs the full stack, from Clash libraries and formal verification to ASIC design.
What is hard to copy is the combination of deep domain knowledge, our own compiler, and formal methods, with software and hardware in one team.
FPGA / ASIC design
Real-time control at microsecond to nanosecond level.
FPGA / ASIC verification
Also offered standalone, with CoCoTB and property-based testing.
Workflow design and setup
Tailored CI pipelines, nightly synthesis and place-and-route, and code-review training.
Clash training and workshops
From single-day workshops to multi-day sessions, with a customer-challenge module.
Blog
How we structure an FPGA design project, from first requirements to verified hardware.
Blog
Hardware technical debt is expensive. Here's how we prevent it from happening with CI, testing, and open-source tooling.
Start here
You talk directly to the engineers who will do the work. Tell us what you are building and where you are stuck, and we will tell you straight whether we are the right fit.