Stay up to date with the latest news and blog articles from QBayLogic.
News
For our 10th anniversary, we asked the people who run QBayLogic what they actually learned. 10 lessons about selling, people and luck, in their own words.
Blog
Bugs, regressions, GHC releases and vendor tool quirks: what it takes to keep Clash, our open-source FPGA compiler, improving, and how we fund the work.
Blog
How we structure an FPGA design project, from first requirements to verified hardware.
Blog
Hardware technical debt is expensive. Here's how we prevent it from happening with CI, testing, and open-source tooling.
Blog
Clash compiles Haskell directly to VHDL and Verilog, with no intermediate step. How functional programming reached the FPGA, and what the trade-off is.
Blog
How eight FPGA nodes synchronised to within 1 ppm without a central clock. Our bittide hardware implementation with Google DeepMind and Stanford, in Clash.
A 3µs deadline at 5000 fps, met on an FPGA. Our RTL for TOmCAT, ESA’s terabit optical link, with TNO and Demcon.
Verification that catches problems early, not late. We rebuilt Axign’s flow around CI and simulation tooling for their next-gen audio chips.
Eight FPGA boards, optically linked, synced to the nanosecond. Our proof-of-concept hardware and software stack for Bittide, Google’s research ...
A low-latency switch carrying four Ethernet streams down one optical fiber, with EtherCAT under a microsecond end to end. QBayLogic’s FPGA fir ...
A steel ball through a spinning disc, every time. Our hard real-time controller for CAES at the University of Twente.
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