You need a digital circuit to do something hard. We help you pick the platform that can do it, then we design it with you. QBayLogic works on FPGA and ASIC design, verification, and the workflow around both. We also created Clash, the compiler our own engineers design in.
We design FPGAs for two jobs:
For TOmCAT we held a 3 microsecond deadline at 5000 frames per second.
We work with high-speed interfaces every day: HBM, DDR3 and DDR4, PCIe, SERDES, and 10G, 25G and 40G Ethernet.
We take digital ASIC work from RTL design through the full RTL to GDSII flow.
That includes macro placement and place-and-route. Our focus there is efficient silicon use and power optimisation.
Both decide what your chip costs to make and to run.
Verification is part of every design we do. But you can also hire us for verification alone, alongside your existing design team.
For Axign we rebuilt verification for their next-generation audio chips around Cocotb, continuous integration and simulation tooling. Problems now surface early instead of late.
A good workflow is the difference between a team that ships and a team that firefights.
We set up the tooling, the automation and the continuous integration around your design process. This is often where we start with a new client. It is also the fastest way to see a difference in day-to-day work.
Clash is our own compiler.
It describes hardware in Haskell, so the model you verify and the design you ship are the same artefact.
We built it, we use it on every project, and we teach it. Our workshops prepare your engineers to develop circuits in it.
OUR CLIENTS
A 3µs deadline at 5000 fps, met on an FPGA. Our RTL for TOmCAT, ESA’s terabit optical link, with TNO and Demcon.
Smart cards with mathematically proven security properties. Our Clash work for EvIT, Cyberagentur’s verification mission.
Verification that catches problems early, not late. We rebuilt Axign’s flow around CI and simulation tooling for their next-gen audio chips.
Eight FPGA boards, optically linked, synced to the nanosecond. Our proof-of-concept hardware and software stack for Bittide, Google’s research ...
A low-latency switch carrying four Ethernet streams down one optical fiber, with EtherCAT under a microsecond end to end. QBayLogic’s FPGA fir ...
A steel ball through a spinning disc, every time. Our hard real-time controller for CAES at the University of Twente.