Mux/Demux – MedTech application
High speed and low latency Ethernet traffic over a specialized optical fiber connection.
QBayLogic is your digital circuit design partner. Our goal is to help you decide which compute platform is right for your application and, together with our partners, create the final product. Our expertise encompasses the following subjects: FPGA design, Digital ASIC design, FPGA/ASIC verification, Workflow design/setup and Clash Workshop & Training. For all other aspects of a complete solution, we have a network of competent partners (see our ChipTech Twente network page).
At QBayLogic, we focus on FPGA design to meet a range of computational needs. Our expertise includes the acceleration of complex algorithms to improve computational efficiency. For control-oriented tasks, we can design systems that operate with real-time constraints at the microsecond to nanosecond level. We have experience with and a deep understanding of high-speed data interfaces, including HBM, DDR3/4, PCIe, SERDES, and 10G/25G/40G Ethernet. Our engineering team works closely with clients to define the specifications and requirements, aiming for an efficient and effective FPGA implementation. With a blend of your domain knowledge and our technical skills, we strive to deliver solid, performance-oriented FPGA designs.
At QBayLogic, we offer a comprehensive suite of Digital ASIC design services, starting from RTL design through to the complete RTL to GDSII flow. Our team is adept at macro placement and place-and-route procedures, focusing on efficient silicon use and power optimization. Design-for-test techniques are integrated into our workflow, including the specific aspect of scan-chain insertion, to facilitate easier testing post-production. In the verification stage, we employ property-based testing and bounded model checking to ensure the design meets all specifications and requirements. Our goal is to work closely with you, combining your domain expertise with our technical skills to produce an effective and reliable ASIC implementation.
While it is always a part of FPGA and ASIC design, we also offer FPGA/ASIC verification as a separate service. We do this in a way that integrates seamlessly with your existing design team’s efforts. We build test frameworks using CoCoTB and Python, bringing added value through our collaboration with the CoCoTB development team for the latest best practices. Our engineers develop generic drivers to facilitate support for a variety of bus and communication protocols, simplifying the verification landscape for your project. For cases where hardware-specific behavior needs to be understood, we use FPGAs as a stand-in for ASICs, delivering not only a closer approximation of the end-product’s functionality but also a significant speed advantage compared to simulation methods. This FPGA-based approach allows for robust early-stage testing before ASIC fabrication. To further refine verification, we make use of property-based testing frameworks like Hedgehog for Haskell and Hypothesis for Python, aiming for exhaustive test coverage. Our team is knowledgeable in using industry-standard simulation programs, such as QuestaSim, Verilator, and Xcelium, to ensure that every aspect of the design is rigorously tested. By providing these services, we aim to enhance the reliability and quality of your design, all while facilitating a smoother verification process for your in-house team.
When you want to make the day-to-day of your team more effective and less frustrating, we can assist in establishing efficient workflow design and setup tailored to your project needs. We specialize in setting up continuous integration pipelines using platforms like GitLab CI, GitHub Actions, or Jenkins. Our workflows make it straightforward to integrate new tests, providing an agile environment for ongoing development. Additionally, synthesis and place & route tasks can be automatically executed in CI and nightly builds, aiding in early problem detection. We also implement caching mechanisms for intermediate build results, aimed at accelerating design iterations. To bolster team proficiency, we offer training in best practices for version control and code review techniques.
We want other engineers to enjoy the benefits of our innovative design method,Clash, which is why we offer specialized training courses to prepare your team for circuit development using Clash. Our training material is based on experience teaching B.Sc. level functional programming and M.Sc. level Computer Architecture classes, and has been adapted to meet the needs of industry professionals. We provide a range of training options, from single-day workshops to multi-day sessions, to fit your team’s availability. These courses come with multiple entry levels, allowing customization based on your team’s existing skills. A standout feature of our workshops is the “customer challenge” module; here, we guide your team through a solution to a specific problem you’re facing, resulting in higher engagement and better material retention. By offering these training sessions, we aim to equip your team with the practical skills needed to efficiently develop circuits using Clash.
We are your business partner for powerful FPGA design and digital design automation. Discover what our innovative and advanced chip solutions can offer you. The more complex the challenge, the more excited we become!