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TOmCAT - FPGA for aerospace communications

Terabit laser communication, first-pass correct

A 3µs deadline at 5000 fps, met on an FPGA. QBayLogic’s RTL design for TOmCAT, ESA’s Terabit Optical Communication Adaptive Terminal, delivered with TNO and Demcon.

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The challenge

Ground-to-satellite optical links need far more bandwidth than radio can carry. As part of ESA’s Terabit Optical Communication Adaptive Terminal (TOmCAT), TNO and Demcon had to capture images at 5000 fps and process every frame in under 3µs.
High-energy laser beams deform as they pass through the atmosphere. Correcting that distortion means measuring and compensating continuously, in a tightly orchestrated pipeline where each incoming sample must be fully processed within 3µs of the sensor producing it.
That deadline rules out a microcontroller or DSP. It needed an FPGA – and the RTL had to be right first time, because one timing miss anywhere in the pipeline breaks the link.

The approach

We started from the math: a precise specification of the operations on each image matrix, before writing a line of hardware.
We turned that specification into an executable model in Clash, our own software-to-hardware compiler, then refined it step by step to match the target device and the real data format.
Because the model, every intermediate stage, and the final design all live in one language, there’s no error-prone hand-off between a reference model and the HDL.

What we verified is what we shipped.

The results

It all came together at delivery:

Every frame processed within the 3µs deadline at 5000 fps. The timing target held across the full pipeline, with no misses to break the link.
First-pass correct: because the verified model and the shipped design are the same artifact, the RTL worked as specified on delivery, with no late respins.
Clash generated standard HDL directly from the optimized design, so it dropped into TNO and Demcon’s existing flow without translation friction.

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• Free-space secure communication • Cryptography • Quantum communication • Bittide / synchronization • Satellite communication

Why QBayLogic?

At QBayLogic, we specialize in designing FPGA architectures for accelerators using a model-based methodology. Our expertise made us the ideal partner to develop the Register-Transfer Level (RTL) design capable of processing high-bandwidth streams on an FPGA, a crucial component of the TOmCAT project. Our approach not only ensured timely delivery and last-but-not least also contributed to the advancement of ground/satellite communication technology.

For more information on the TOmCAT project, visit ESA’s website.
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