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Blog
As it happens, I had been working on a project to exchange data packets between the FPGA (in Clash) and the HPS on a Terasic DE10-Standard.
Blog
For this tutorial, you will need at least Clash version 1.6.3. We’ll be programming the Terasic DE0-Nano FPGA development board using the functional hardware description language Clash.
News
It’s here! Clash 1.0 is finally released! And it has a binary release for the very first time! Check out the install instructions on how to get it!
Blog
I.e. it cannot solve constraints involving subtraction (-) or user-specified type-level operations on type-level naturals […] For user-defined type-level natural operations, we are currently out of luck.
Blog
If you have ever worked with GHC.TypeLits then you have probably encountered an error that is very similar to...
Blog
Since version 7.10.2, GHC supports so-called type-checker plugins which let us extend GHC’s constraint solver, i.e. extend the range of programs GHC can type check.
A 3µs deadline at 5000 fps, met on an FPGA. Our RTL for TOmCAT, ESA’s terabit optical link, with TNO and Demcon.
Verification that catches problems early, not late. We rebuilt Axign’s flow around CI and simulation tooling for their next-gen audio chips.
Eight FPGA boards, optically linked, synced to the nanosecond. Our proof-of-concept hardware and software stack for Bittide, Google’s research ...
A low-latency switch carrying four Ethernet streams down one optical fiber, with EtherCAT under a microsecond end to end. QBayLogic’s FPGA fir ...
A steel ball through a spinning disc, every time. Our hard real-time controller for CAES at the University of Twente.
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